The power consumption in a static random access memory (SRAM) is highly dependent on the voltages applied to bit lines, such that as the amplitude of the voltages applied to the bit lines increases, power consumption increases. Hereinafter, this voltage amplitude is referred to as “BL amplitude.” In general, BL amplitude of the voltages that can be used in operating a SRAM is known to be highly dependent on the particulars of the manufacturing process of the SRAM.
Due to this fabrication process dependency, the BL amplitude is set, in design, so as to enable readout of data under the worst condition (i.e., the minimally acceptable fabrication result) in which case the acceptable BL amplitude is small. However, since the BL amplitude is larger than the required minimum amplitude for SRAM that exceeds the minimally acceptable fabrication result (e.g., for the ideal or best condition) the power consumption of the SRAM would be excessive.
A timing adjustment method using a dummy cell has previously been proposed to reduce power consumption in such a situation. However, a difference in power consumption between an SS (slow-slow) process SRAM and an FF (fast-fast) process SRAM becomes a problem with this method. Here, “SS process” and “FF process” are terms related to the processing variation of the SRAM resulting from differences in fabrication.
The decreasing of a driving current for a metal-oxide-semiconductor field-effect transistor (MOSFET) is referred to as the “SS process”, and the increasing of a driving current for a MOSFET is referred to as the “FF process” A difference in driving current between the SS process and the FF process SRAM occurs due to, for example, a variation of the threshold voltage of a MOSFET, which causes a variation in BL amplitude.